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The following paragraphs are from an article in ComputerWorld about the Power6 chip. It speaks of a built in failover ability right in the chip. Can anyone shed more light on this subject and why IBM has made no mention of it in their briefings to the i crowd. Shane. ------------------------ Power6 watches gross indicators such as thermometers, fan tachometers, and parity bits just like x86 does, but Power6’s microcode is loaded with little sanity checks. The Power6 CPU analyses the consistency of the states of its various modules, and if it finds a mismatch, it takes fine-grained action ranging from retrying a failed instruction to reverting to a known, healthy state. If an invalid state persists, Power6 recovers by moving in-process workload to a healthy CPU. This isn’t something that Power6 does in its idle time. It does it with every clock cycle, 4.7 billion times each second.